Nonvolatile memory cells for performing write operation by storing charge in a floating gate electrode, hereinafter referred to as FG (floating gate) type memory cells, are widely used. On the other hand, there is constantly a strong demand for increasing the storage capacity of semiconductor memories.
In view of increasing the integration density of FG type memory cells, it is necessary to narrow the spacing between a plurality of floating gate electrodes provided via a tunnel insulating film on the surface of a semiconductor substrate. However, if the spacing between the floating gate electrodes is narrowed, then when a control gate electrode is formed on the floating gate electrode, filling failure may occur between the floating gate electrodes, or variation may occur in the gate resistance of the control gate electrode, causing the problem of malfunctions in memory cells.
On the other hand, the method of narrowing the floating gate electrode to ensure the electrode spacing is also effective in increasing the integration density of FG type memory cells. However, if the electrode width is narrowed, the aspect ratio of the cross-sectional shape of the floating gate electrode increases. This floating gate electrode easily falls down during processing or the subsequent cleaning step, and results in decreasing the manufacturing yield. For instance, in the case where the floating gate electrode has a height of approximately 60 nm, if the width of the floating gate electrode is 30 nm or less, the yield decrease due to collapse becomes non-negligible. Furthermore, if the width is 20 nm or less, forming the cell structure is in itself difficult. This places a technical limit to the floating gate electrode.
In view of avoiding the above problems, the method for forming the interelectrode insulating film provided between the floating gate electrode and the control gate electrode is important.